Data input to a binary encoder is conventionally from an n-bit bus, for n an even integer greater than zero. The data input may be what is known as “one-hot” data. “One-hot” data includes all data input bits being inactive except for one bit which is active. Conventionally, inactive bits are represented as binary zeros, and the active bit is represented as a binary one. Data input to a binary encoder is converted or encoded into a binary address of length log n to the base two (i.e., log2 n).
In contrast, data input to a priority encoder, conventionally from an n-bit bus, has one or more active bits. A priority encoder is configured to determine which of the n-bits has the highest priority, which is more problematic when more than one bit is active. A highest priority determination is made using a set of rules. Moreover, highest priority may be based either on the most significant bit (“MSB”) or the least significant bit (“LSB”). Output of a priority encoder may drive control signaling or may be represented as a one-hot output bus. With respect to the later embodiment, a one-hot output bus conventionally will have the one active bit in the same location as the bit of highest priority in the n-bit input bus.
A conventional binary encoder receives one-hot data to derive a binary output address. For example, if the active bit is found in an odd location, then the resulting address will be odd. The conventional binary encoder may be configured to set the lowest output bit active responsive to a resulting address being odd. However, this will not result in correct functionality if the n-bit input bus has multiple bits that are logic high because these logic high bits will start to interfere with each other in the address calculation tree or trees. For example, there may be active bits in odd locations resulting in an odd output address, even though the highest priority address may actually be even. Thus, the output result may be for an address that does not have an active bit set, i.e., aliasing.
To avoid aliasing as described in the preceding paragraph, heretofore a two-tier calculation was done. The first tier generates a one-hot address using a priority encoder. The one-hot address is used in the second tier, where a binary encoder using the one-hot address from the first tier, generates a binary address. Thus, conventionally two tiers were used to take a binary address from an n-bit input and convert it to a highest priority address. These two tiers may mean that: clock cycle time may have to be extended if both priority encoding and binary encoding are done in one clock cycle; or two clock cycles may be needed if priority encoding and binary encoding are pipelined.
Both a priority encoder and a binary encoder use complete input busing to calculate their respective outputs. For example, the lowest priority bit of a one-hot calculation is only active when the input bit at that same location is active and every other input bit is inactive. Likewise, the lowest address bit in a binary address is active when the binary address is odd. Therefore, every odd bit resulting from a one-hot calculation conventionally is examined to determine if the lowest address should be active. In short, this means that implementing a priority encoder and a binary encoder to convert a binary address from an n-bit input to a priority address for n equal to eight or more involves a significant number of signals being routed to multiple destinations for independent calculations. Such routing may result in additional signal delay causing a lowering of frequency of operation, place and route runtime, and delay due to an increase in non-deterministic parasitic capacitive coupling.
Accordingly, it would be desirable to provide conversion of a binary address from an n-bit input to a priority address that avoids or reduces one or more of the above-mentioned limitations.